For past few years i have been working with quite a few ARM simulators, like Keil uVision or Trace32. Although these tools are very capable (T32 especially) I decided to create my very own Instruction Set Simulator (ISS), simply because I can, like and i don’t have money for professional software :).
First thing that really took my time were the goals:
– should I create ISS with single step functionality or single core clock tick precision. Having to emulate CM3 clock i would need to take into account whole CPU architecture including accurate pipelining implementation. For now I will stick with single step option, although I will have in mind future expansion in mind while designing classes.
– another thing that confuse me was the memory model. Should it be static array or some kind of dynamic structure? After fixed memory solution speaks simplicity and fast memory address calculations, although it would consume quite a lot memory. Having to put such array on stack would easily result in stack overflow and putting it on the heap would take down ~4Gb or RAM. Of course in reality no one would do such thing since MCUs use rather small values like 512kb for data/code and 64kb for RAM, but that would limit user to reduced memory addressable space and make it hard when mapping peripheral devices. On the other hand, availability of full address space wouldn’t really give significant advantage to user in real-life scenarios.
The solution i came up with is flash like abstraction of data structure, where memory is accessed as pages/block chunks. The performance gain compared to using STD containers is very noticeable (in seconds).
The next thing is:
– since I am used to work with Lauterbach Trace32 i have high demands for simulation software, like easy peripheral models development, wide breakpoints options and data/memory view (how the hell did Keil uVision screw up memory dump so much compared to T32?).
– I am currently fighting with overall design, The biggest problem is the API, because i have in mind, creating IDE for hardware debugging on re-programmable FPGA (or CPLD) as programmer with JTAG for both 2×10 and cortex 10 pin interface.