Overview based on Cortex™-M3 Devices
Generic User Guide (ARM DUI 0552A (ID121610).

Cortex-M3 implementation
Cortex-M3 implementation

3 stage pipeline, Harvard arch.. IEEE-754 single-precision floating point op.

1. Cortex-M3 core peripherals
– Nested Vectored Interrupt Controller
– System Control Block
– System Timer (used for RTOS or timer)
– Memory Protection Unit (allow defining the memory attributes for
up to 8 different memory regions)

2. Processor mode and privilege levels for software execution
The processor modes are:
Thread mode Used to execute application software. The processor enters Thread mode
when it comes out of reset.
Handler mode Used to handle exceptions. The processor returns to Thread mode when it
has finished all exception processing.

The privilege levels for software execution:
– Unprivileged/user level
The software:
• has limited access to the MSR and MRS instructions, and cannot use the
CPS instruction
• cannot access the system timer, NVIC, or system control block
• might have restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
– Privileged
The software can use all the instructions and has access to all resources.
Privileged software executes at the privileged level.

RTOS will run in privileged mode and user program run by it, in unprivileged mode.
When interrupt is being handled by MCU it is always working in Handler mode, even if it occurred in unprivileged part of code.
MCU always start in privileged mode, so it’s RTOS job to set unprivileged mode when it is ready. Application ran in unprivileged mode can’t change mode to privileged mode (since it doesn’t has access to CONTROL register). Of course when interrupt occurs, routine is being handled in privilege mode.

CONTROL register
CONTROL register

SPSEL – Currently active stack pointer (In Handler mode this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return):
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer. (only in Thread mode. Interrupts are always using MSP)
nPRIV – Thread mode privilege level:
0 = Privileged
1 = Unprivileged.

3. Stack

The processor uses a full descending stack (LIFO – Last In First Out).

Summary of processor mode, execution privilege level, and stack use options
Summary of processor mode, execution privilege level, and stack use options

Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register
indicates the stack pointer to use:
• 0 = Main Stack Pointer (MSP). This is the reset value.
• 1 = Process Stack Pointer (PSP).

User can access stack by using PUSH and POP instructions. PUSH will decrement the SP and POP will increase it.

Thanks to two stacks, user application in unprivileged mode won’t corrupt main stack.

In privileged mode system can use MRS and MSR instruction to directly access SP. In STM firmware it is possible to use pre-defined macros like: __set_PSP( uint32 )/__set_MSP( uint32 ) and __get_PSP()/__get_MSP().